Mixed Signals
Any sufficiently advanced information is indistinguishable from noise
Monday 17 March 2008, 7:35 PM
Intel slips out a few teasers on six-core, Nehalem, 32nm
Intel's priming the PR pump prior to IDF Spring in a couple of week's time, with a set of announcements about Nehalem, Sandy Bridge and Larrabee. I got on the blower to a telephone conference with various Intelites to find out more.
But first, Dunnington. As expected, this is a six core, one die Penryn-based chip, with 16MB of level 3 cache and compatibility with the Caneland socket and power envelope – 80 watts.. It's already being demonstrated, and will be available in the second half of 2008.
Nehalem next. This is the first major redesign of the Core architecture for 45nm, and Stephen Smith, Vice President and Director of Digital Enterprise Group Operations (as the transistors get smaller, the titles get bigger) was keen to emphasis how modular it was. The components – the CPU cores, the QuickPath Interconnect, the integrated memory controller, even onboard graphics –can be combined in various ways to meet various needs.
The core itself contains “33 percent more parallelism”, according to a washing-powder style starburst on the Powerpoint presentation. This translates to it being able to hold 128 instructions 'on the fly' – in other words, in various states of getting processed and available for inspection – as opposed to 96 in the previous cores. That's mostly because the Nehalem core can decode four instructions per gulp in parallel, as opposed to three before, and can stack 'em up 32 deep.
Nehalem also has Simultaneous Multi-Threading (SMT), which is the descendent of Hyper-Threading. Few details are available yet, except that each core will manage two threads simultaneously, and various algorithmic improvements and extra cache will make it especially good for (you may already have guessed) database work and multimedia.
Ah yes, the cache. Nehalem has a new 3rd level 8MB cache with an inclusive policy. That means that everything that's in the first and second level caches has to be in the third level too – making it much faster for the cores to find out whether the data they need is available. It also means that cores don't have to go snooping around all the other cores – everything's in one place -= which has significant power and performance implications, especially if you're modular and can have lots of cores. Like Nehalem. All this is due towards the end of 2008.
Sandy Bridge is due in 2010, and will be the second 32nm chip (the first, Westmere, is a compaction of Nehalem). Intel's still not saying much about Sandy Bridge, but it is giving advance notice of a major upgrade to the instruction set that comes with it. Advanced Vector Extentiosn (AVX) is a super-sized SIMD: SIMD is 128 bits wide, enough for four single precision or two double precision floating point numbers. AVX is double this, which increases throughput and energy efficiency. Moreover, other changes to the architecture will improve code size – full details are due at IDF.
Finally, Intel promised a 2008 demonstration of Larrabee, although it didn't give out any new information. It did say that it thought ray-tracing – sorry, Visual Computing – was going to be the way ahead, instead of polygon rendering, and that Larrabee would be very good at ray-tracing – sorry, Visual Computing.
There was other stuff about Itanium and power benchmarking and tools and ticks and tocks, but nothing you haven't heard before. And I'm going to look a bit more closely at QuickPath, Intel's new interconnect, because it's got some intriguing fault-tolerance capabilities. It's interesting for another reason: with Itanium and Xeon sharing the same interconnects and memory controllers, where's the magic?
Week after next, in Shanghai!
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