Atom Power – part 2

Had some time today to re-assess what I had learned yesterday about the Atom. The most astounding item might be that Intel has done an about-face in attitude and discovered that there really is a market for low power x86 based systems on a chip. They pretty much had abandoned the embedded market previously when they off-loaded their Xscale, the legacy 8051 line and the 960 special processors. Too bad they had to more or less let Via and AMD pretty much write their own tickets. Negroponte might have started an un-intentional trend with his OLPC and to be honest I'm glad. Regardless, the collision between the green trend( smaller/cooler) and the technology(-solves-our-problems) movement has finally borne good solid techno-fruit.

I apologize somewhat for the wack rant about the Intel presentation yesterday but I can blame it on 5 hours of driving and “White-line” fever (actually yellow-black-concrete-tan, yellow-black...enough of that!). The comments about St. Moore however were dead on. The poor guy gets moore grief about “his law”!

Back to the chip...

What's really weird is that the CPU chip is really not that remarkable. However it is basically a superPentiumM chip with really tight power management capabilities unseen in any previous Pentium 4 or M series CPU. Especially the C6 mode (I called it Rip Van Winkle) described earlier.

What is really cool is the SCH or ISCH, Intel System Controller Hub chip. All of the peripheral I/O capability is built into the SCH that runs at least on the front bus at same speed as the 1GByte DDR2 maximum ram. The system memory controller is on the SCH along with the system I/O so its like a Northbridge/Southbridge combination. The combination of the Atom CPU and the ISCH is a complete 2 chip PC system that runs with a execution of one command per clock cycle. Although the ISCH will only support a single CPU it enables 2 logical (virtual) CPUs using the Hyperthreading functions. Datapath is 64 bits wide.

I/O that is supported simultaneously* by the SCH includes:

Integrated Graphics and Video processor supported by LVDS
A second Integrated Graphics and Video processor supported by SDVO (includes HD/SD/HDMI)
Supported display resolutions are 1600 x 1400 on one and 1280 x 1024 with 18 bit and 24 bit color. The rectangular orientation is independently programmable with either tall vertical portrait or wide landscape displays.

Intel High Definition Audio 32bit/192kHz sample rate on 2 incoming streams and 2 outgoing streams

3 UHCI USB 1.1 controllers and one EHCI USB 2.0 controller supporting 6 high/low speed data transfers, 2 high speed only ports for use only on-board the system pcb (a socket with an directly attached device probably could work). One port can also be programmed to operate as a USB client.

2 PCI Express root ports configured as 2 x1 lanes, each port supports 2.5 Gbytes /second bidirectionally.

A PATA (parallel ATA port) that can support PIO, DAM in ATA-5 up 66MB/s and UltraDMA 100/66/33. Although not obvious, this port can be setup to directly tie to an on-board Flash Memory controller chip that manages standard Intel Flash memory modules that operate as an IDE-like hard drive. One of the presentations described a new Nand-Nor Flash technology that Intel was announcing and as feature for designs using the Atom.

3 separate SDIO/MMC expansion ports for additional serial formatted memory.

SMBus Host Controller that will also support I2C devices.

14 General Purpose I/O pins running at CPU core voltages so that will need an external voltage level shift interface chip.

*simultaneously – meaning that ALL of the listed functions are supported without multiplexing or programmable pin assignments, both common in small 8 and 16 bit microprocessors. This is not a 8051!